1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) employing an SOI (Silicon-On-Insulator) substrate and a method of manufacturing the same.
2. Description of the Background Art
Attention has been given to a semiconductor device (SOI device) employing an SOI substrate as a high-operating-speed, low-power-consumption device. The SOI substrate has a multi-layer structure including a semiconductor substrate, an insulation layer and a semiconductor layer which are stacked in the order named. An SOI device (thin-film SOI device) having a semiconductor layer thinned to about several micrometers has recently received particular attention, and has been expected to be applied to LSI circuits for portable equipment.
FIG. 44 is a sectional view showing a structure of a background art semiconductor device. An SOI substrate 104 has a multi-layer structure such that a silicon substrate 101, a BOX (Buried OXide) layer 102 and a silicon layer 103 are stacked in the order named. An isolating insulation film 105 made of silicon oxide is partially formed in the silicon layer 103. The isolating insulation film 105 extends from the upper surface of the silicon layer 103 to the upper surface of the BOX layer 102. The isolating insulation film having such a configuration is referred to as a xe2x80x9ccompletely isolating insulation film.xe2x80x9d
A MOSFET is formed in a device region defined by the isolating insulation film 105 in a manner to be specifically described below. A silicon oxide film 106 is formed partially on the upper surface of the silicon layer 103. A gate electrode 107 made of polysilicon is formed partially on the silicon oxide film 106. A portion of the silicon oxide film 106 which lies under the gate electrode 107 functions as a gate insulation film. A silicon nitride film 109 is formed on each side surface of the gate electrode 107, with a silicon oxide film 108 therebetween. The silicon oxide films 108 are formed not only between the side surfaces of the gate electrode 107 and side surfaces of the silicon nitride films 109 but also between the upper surface of the silicon oxide film 106 and the lower surface of the silicon nitride films 109.
A pair of source/drain regions 110 are formed in the silicon layer 103. A region between the pair of source/drain regions 110 is defined as a body region 112. Each of the source/drain regions 110 has an extension 111 extending to under the gate electrode 107 in the upper surface of the silicon layer 103.
FIG. 45 is a sectional view showing a structure of another background art semiconductor device. The semiconductor device shown in FIG. 45 has an isolating insulation film 130 made of silicon oxide in place of the completely isolating insulation film 105 shown in FIG. 44. The lower surface of the isolating insulation film 130 does not reach the upper surface of the BOX layer 102. The isolating insulation film having such a configuration is referred to as a xe2x80x9cpartially isolating insulation film.xe2x80x9d The remaining structure of the semiconductor device shown in FIG. 45 is similar to the corresponding structure of the semiconductor device shown in FIG. 44.
FIG. 46 is a schematic top plan view showing a top surface structure of the semiconductor device shown in FIG. 45. The use of the partially isolating insulation film 130 allows the body region 112 to be tied to a fixed potential through a portion of the silicon layer 103 which lies between the lower surface of the isolating insulation film 130 and the upper surface of the BOX layer 102 from a body contact region 150. This suppresses a so-called floating body effect such as the occurrence of a kink effect and variations in delay time depending on an operating frequency.
Referring again to FIGS. 44 and 45, the width W101 of the silicon oxide film 108 in a direction of the gate length (or in the lateral direction as viewed in the drawings) is less than the total thickness T101 of the silicon oxide film 106 and the silicon oxide film 108. In some cases, however, a portion of the silicon oxide film 106 other than functioning as the gate insulation film (i.e., a portion of the silicon oxide film 106 which lies between the lower surface of the silicon oxide film 108 and the upper surface of the silicon layer 103 as viewed in FIG. 44) is removed away during a gate etching process, in which case the width W101 is equal to the total thickness T101. Thus, the width W101 is not greater than the total thickness T101 in the background art semiconductor devices.
Unfortunately, in such background art semiconductor devices, the relatively small width W101 of the silicon oxide film 108 results in a relatively short distance L101 between the pair of source/drain regions 110 (more specifically, between the pair of extensions 111).
In the semiconductor devices shown in FIGS. 44 and 45, there is a parasitic bipolar transistor with the source/drain regions 110 serving as an emitter and a collector and the body region 112 serving as a base. The short distance L101 between the pair of source/drain regions 110 means a small base width of the parasitic bipolar transistor, resulting in high gain of the parasitic bipolar transistor. As a result, the background art semiconductor devices present a problem such that there is a danger that the high gain of the parasitic bipolar transistor causes a malfunction and a variation in operating characteristics of the MOSFET.
It is an object of the present invention to provide a semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same.
According to a first aspect of the present invention, the semiconductor device includes an SOI substrate, a first insulation film, a gate electrode, a pair of second insulation films, a pair of third insulation films, a body region, and a pair of source/drain regions. The SOI substrate has a multi-layer structure including a semiconductor substrate, an insulation layer and a semiconductor layer stacked in the order named. The first insulation film is formed on a main surface of the semiconductor layer. The gate electrode is formed on the first insulation film. The pair of second insulation films have respective inner side surfaces in contact with side surfaces of the gate electrode and respective outer side surfaces out of contact with the side surfaces of the gate electrode, with the gate electrode disposed between the pair of second insulation films. The pair of third insulation films are formed on the main surface of the semiconductor layer, with the first insulation film therebetween. The pair of third insulation films have respective inner side surfaces in contact with the outer side surfaces of the second insulation films and respective outer side surfaces out of contact with the outer side surfaces of the second insulation films, with the gate electrode and the second insulation films disposed between the pair of third insulation films. The body region is formed in the semiconductor layer under the gate electrode. The pair of source/drain regions are formed in the semiconductor layer, with the body region disposed between the pair of source/drain regions. The source/drain regions have respective extensions extending from under the outer side surfaces of the second insulation films toward the body region in the main surface of the semiconductor layer. The width of the second insulation films in a direction of gate length is greater than the thickness of a portion of the first insulation film underlying the third insulation films.
In the semiconductor device according to the present invention, the relatively large width of the second insulation films leads to a relatively long distance between the pair of extensions formed by ion implantation using the second insulation films as an implant mask. Accordingly increased base width of a parasitic bipolar transistor reduces the gain of the parasitic bipolar transistor, thereby to suppress malfunctions and operating characteristic variations of the MOSFET. Additionally, a decreased amount of overlap between the gate electrode and the extensions as viewed in plan suppresses a gate overlap capacitance to achieve the increase in operating speed and the reduction in power consumption.
Preferably, in the semiconductor device, the width of the second insulation films is in the range of {fraction (2/7)} to 1 times the gate length.
The semiconductor device achieves the stable formation of the gate electrode and suppresses the reduction in maximum oscillation frequency.
Preferably, in the semiconductor device, a lifetime killer is formed in the main surface of the semiconductor layer.
The semiconductor device, in which the lifetime killer for the parasitic bipolar transistor is formed in the main surface of the semiconductor layer, reduces the gain of the parasitic bipolar transistor.
Preferably, in the semiconductor device, a portion of the main surface of the semiconductor layer on which the third insulation films are formed is sunk toward the insulation layer below a portion of the main surface of the semiconductor layer on which the second insulation films are formed.
In the semiconductor device, etching the upper surface of the semiconductor layer as well in the etching step for the formation of the second insulation films creates the lifetime killer in the main surface of the semiconductor layer.
Preferably, in the semiconductor device, a portion of the main surface of the semiconductor layer positioned outside the outer side surfaces of the third insulation films is sunk toward the insulation layer below a portion of the main surface of the semiconductor layer on which the third insulation films are formed.
In the semiconductor device, etching the upper surface of the semiconductor layer as well in the etching step for the formation of the third insulation films creates the lifetime killer in the main surface of the semiconductor layer.
Preferably, the semiconductor device further includes a metal-semiconductor compound layer formed on the source/drain regions.
In the semiconductor device, forming the metal-semiconductor compound layer on the source/drain regions creates the lifetime killer in the main surface of the semiconductor layer.
Preferably, in the semiconductor device, the third insulation films are made of silicon nitride. The third insulation films are formed directly on the main surface of the semiconductor layer without the first insulation film therebetween.
In the semiconductor device, stresses caused at an interface between the silicon nitride film and the semiconductor layer create the lifetime killer in the main surface of the semiconductor layer.
Preferably, the semiconductor device is a MOSFET. The MOSFET includes an NMOSFET and a PMOSFET both formed in the semiconductor layer. The width of the second insulation films included in the NMOSFET is greater than the width of the second insulation films included in the PMOSFET.
The semiconductor device suppresses a floating body effect problem in the NMOSFET to achieve the increase in operating speed and an improvement in current driving capability.
Preferably, the semiconductor device is a MOSFET. The MOSFET includes an NMOSFET and a PMOSFET both formed in the semiconductor layer. The width of the second insulation films included in the PMOSFET is greater than the width of the second insulation films included in the NMOSFET.
The semiconductor device suppresses the occurrence of a short channel effect in the PMOSFET. This improves the roll-off characteristic of the PMOSFET to suppress the increase in off-state current, thereby achieving the reduction in power consumption.
According to a second aspect of the present invention, the semiconductor device includes a substrate, a first semiconductor element, and a second semiconductor element. The substrate has a first region with a digital circuit formed therein, and a second region with an analog or RF (radio frequency) circuit formed therein. The first semiconductor element is formed in the first region and constitutes the digital circuit. The second semiconductor element is formed in the second region and constitutes the analog or RF circuit. The first semiconductor element includes a first gate electrode formed on a main surface of the substrate, with a first gate insulation film therebetween, a first body region formed in the substrate under the first gate electrode, and a pair of first source/drain regions formed in the substrate, with the first body region disposed between the pair of first source/drain regions. The second semiconductor element includes a second gate electrode formed on the main surface of the substrate, with a second gate insulation film therebetween, a second body region formed in the substrate under the second gate electrode, and a pair of second source/drain regions formed in the substrate, with the second body region disposed between the pair of second source/drain regions. The pair of first source/drain regions have a pair of first extensions, respectively, extending toward under the first gate electrode in the main surface of the semiconductor layer. The pair of second source/drain regions have a pair of second extensions, respectively, extending toward under the second gate electrode in the main surface of the semiconductor layer. The amount of overlap between the first gate electrode and the first extensions as viewed in plan is greater than the amount of overlap between the second gate electrode and the second extensions.
The semiconductor device reduces an effective channel length to shorten delay time, thereby improving the performance for the first semiconductor element constituting the digital circuit.
Preferably, in the semiconductor device, the first semiconductor element further includes a first sidewall formed on a side surface of the first gate electrode. The second semiconductor element further includes a first insulation film formed on a side surface of the second gate electrode, and a second sidewall formed on the side surface of the second gate electrode, with the first insulation film therebetween.
In the semiconductor device, performing ion implantation to form the second extensions after the first insulation film serving as an offset insulation film is formed suppresses a gate overlap capacitance for the second semiconductor element constituting the analog or RF circuit.
Preferably, in the semiconductor device, the first semiconductor element further includes a second insulation film formed between the first gate electrode and the first sidewall, the second insulation film being in contact with the side surface of the first gate electrode. The first insulation film includes a third insulation film formed in contact with the side surface of the second gate electrode, the third insulation film being equal in thickness to the second insulation film, and a fourth insulation film formed between the third insulation film and the second sidewall.
In the semiconductor device, performing ion implantation to form the first extensions after the second insulation film serving as an offset insulation film is formed suppresses a gate overlap capacitance for the first semiconductor element constituting the digital circuit.
According to a third aspect of the present invention, the semiconductor device includes a substrate, a semiconductor element, an interlayer insulation film, and a gate interconnect line. The semiconductor element includes (a) a gate electrode formed on a main surface of the substrate, with a gate insulation film therebetween, and extending in a predetermined direction, (b) a first sidewall formed on a side surface of the gate electrode, (c) a body region formed in the substrate under the gate electrode, and (d) a pair of source/drain regions formed in the substrate, with the body region disposed between the pair of source/drain regions. The interlayer insulation film is formed on the substrate to cover the semiconductor element. The gate interconnect line is in contact with an upper surface of the gate electrode and extends in the predetermined direction, the gate interconnect line being formed in the interlayer insulation film. A dimension of the gate interconnect line in a direction of gate length of the gate electrode is greater than the gate length of the gate electrode.
The semiconductor device decreases a gate resistance to increase the maximum oscillation frequency of the semiconductor element.
Preferably, the semiconductor device further includes a second sidewall formed on the side surface of the gate electrode, with the first sidewall therebetween.
In the semiconductor device, the formation of the second sidewall improves a misalignment margin in manufacturing steps of the semiconductor device.
Preferably, in the semiconductor device, a dimension of the second sidewall in the direction of the gate length is greater than a dimension of the first sidewall in the direction of the gate length.
The semiconductor device further improves the misalignment margin in the manufacturing steps of the semiconductor device.
Preferably, the semiconductor device further includes a contact plug connected to the source/drain regions and formed in the interlayer insulation film. The dimension of the gate interconnect line in the direction of the gate length is less than a dimension of the contact plug in the direction of the gate length.
The semiconductor device reduces an etch rate difference when forming a contact hole for the contact plug and an interconnect trench for the gate interconnect line in the same etching step in the manufacturing process of the semiconductor device.
According to a fourth aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (a) to (g). The step (a) is to prepare an SOI substrate having a multi-layer structure including a semiconductor substrate, an insulation layer and a semiconductor layer stacked in the order named. The step (b) is to form a first insulation film on a main surface of the semiconductor layer. The step (c) is to form a gate electrode on the first insulation film. The step (d) is to form a pair of second insulation films having respective inner side surfaces in contact with side surfaces of the gate electrode and respective outer side surfaces out of contact with the side surfaces of the gate electrode, with the gate electrode disposed between the pair of second insulation films, the width of the second insulation films in a direction of gate length being greater than the thickness of the first insulation film. The step (e) is to introduce an impurity into the main surface of the semiconductor layer to form a pair of extensions, the step (e) being performed after the step (d). The step (f) is to form a pair of third insulation films having respective inner side surfaces in contact with the outer side surfaces of the second insulation films and respective outer side surfaces out of contact with the outer side surfaces of the second insulation films, with the gate electrode and the second insulation films disposed between the pair of third insulation films. The step (g) is to introduce an impurity into the semiconductor layer to form a pair of source/drain regions, the step (g) being performed after the step (f).
In the method according to the present invention, the relatively large width of the second insulation films leads to a relatively long distance between the pair of extensions formed in the step (e). Accordingly increased base width of a parasitic bipolar transistor reduces the gain of the parasitic bipolar transistor, thereby to suppress malfunctions and operating characteristic variations of the MOSFET. Additionally, a decreased amount of overlap between the gate electrode and the extensions as viewed in plan suppresses a gate overlap capacitance to achieve the increase in operating speed and the reduction in power consumption.
Preferably, in the method, the width of the second insulation films formed in the step (d) is in the range of {fraction (2/7)} to 1 times the gate length.
The method achieves the stable formation of the gate electrode and suppresses the reduction in maximum oscillation frequency.
Preferably, the method further includes the step of (h) forming a lifetime killer in the main surface of the semiconductor layer.
The method, in which the lifetime killer for the parasitic bipolar transistor is formed in the main surface of the semiconductor layer, reduces the gain of the parasitic bipolar transistor.
Preferably, in the method, the step (h) includes the step of etching a portion of the main surface of the semiconductor layer on which the third insulation films are formed.
In the method, etching the portion of the main surface of the semiconductor layer on which the third insulation films are formed creates the lifetime killer in the main surface of the semiconductor layer.
Preferably, in the method, the step (h) includes the step of etching a portion of the main surface of the semiconductor layer positioned outside the outer side surfaces of the third insulation films.
In the method, etching the portion of the main surface of the semiconductor layer positioned outside the outer side surfaces of the third insulation films creates the lifetime killer in the main surface of the semiconductor layer.
Preferably, in the method, the step (h) includes the step of forming a metal-semiconductor compound layer on the source/drain regions.
In the method, forming the metal-semiconductor compound layer on the source/drain regions creates the lifetime killer in the main surface of the semiconductor layer.
Preferably, in the method, the third insulation films are made of silicon nitride, and the step (h) includes the step of forming the third insulation films directly on the main surface of the semiconductor layer.
In the method, stresses caused at an interface between the silicon nitride film and the semiconductor layer create the lifetime killer in the main surface of the semiconductor layer.
Preferably, in the method, the semiconductor device is a MOSFET. The MOSFET includes an NMOSFET and a PMOSFET both formed in the semiconductor layer. The step (d) includes the steps of: (d-1) forming the second insulation films having a first width in a region in which the PMOSFET is to be formed; and (d-2) forming the second insulation films having a second width greater than the first width in a region in which the NMOSFET is to be formed.
The method suppresses a floating body effect problem in the NMOSFET to achieve the increase in operating speed and an improvement in current driving capability.
Preferably, in the method, the semiconductor device is a MOSFET. The MOSFET includes an NMOSFET and a PMOSFET both formed in the semiconductor layer. The step (d) includes the steps of: (d-1) forming the second insulation films having a first width in a region in which the NMOSFET is to be formed; and (d-2) forming the second insulation films having a second width greater than the first width in a region in which the PMOSFET is to be formed.
The method suppresses the occurrence of a short channel effect in the PMOSFET. This improves the roll-off characteristic of the PMOSFET to suppress the increase in off-state current, thereby achieving the reduction in power consumption.
According to a fifth aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (a) to (f). The step (a) is to prepare a substrate having a first region in which a digital circuit is to be formed, and a second region in which an analog or RF circuit is to be formed. The step (b) is to form a first gate electrode on a main surface of the substrate in the first region, with a first gate insulation film therebetween, and a second gate electrode on the main surface of the substrate in the second region, with a second gate insulation film therebetween. The step (c) is to form a first insulation film on a side surface of the second gate electrode. The step (d) is to form a first sidewall on a side surface of the first gate electrode, and a second sidewall on the side surface of the second gate electrode, with the first insulation film therebetween. The step (e) is to introduce an impurity into the main surface of the substrate in the first region to form a pair of first extensions extending toward under the first gate electrode, the step (e) being performed before the step (d). The step (f) is to introduce an impurity into the main surface of the substrate in the second region to form a pair of second extensions extending toward under the second gate electrode, the step (f) being performed after the step (c) and before the step (d).
The method reduces the effective channel length of a semiconductor element constituting the digital circuit to shorten delay time, thereby improving the performance. Additionally, forming the second extensions in the step (f) after the first insulation film serving as an offset insulation film is formed in the step (c) suppresses a gate overlap capacitance for a semiconductor element constituting the analog or RF circuit.
Preferably, the method further includes the step of (g) forming a second insulation film in contact with the side surface of the first gate electrode, the step (g) being performed before the step (e). The step (c) includes the steps of (c-1) forming a third insulation film in contact with the side surface of the second gate electrode, the step (c-1) being performed in the same step as the step (g), and (c-2) forming a fourth insulation film on the side surface of the second gate electrode, with the third insulation film therebetween.
In the method, forming the first extensions in the step (e) after the second insulation film serving as an offset insulation film is formed in the step (g) suppresses a gate overlap capacitance for the semiconductor element constituting the digital circuit.
According to a sixth aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (a) to (e). The step (a) is to prepare a substrate. The step (b) is to form a gate electrode extending in a predetermined direction on a main surface of the substrate, with a gate insulation film therebetween. The step (c) is to form a first sidewall on a side surface of the gate electrode. The step (d) is to form an interlayer insulation film on the substrate to cover the gate electrode and the first sidewall. The step (e) is to form a gate interconnect line in the interlayer insulation film, the gate interconnect line being in contact with an upper surface of the gate electrode and extending in the predetermined direction, wherein a dimension of the gate interconnect line in a direction of gate length of the gate electrode is greater than the gate length of the gate electrode.
The method provides a semiconductor device which decreases a gate resistance to increase the maximum oscillation frequency.
Preferably, the method further includes the step of (f) forming a second sidewall on the side surface of the gate electrode, with the first sidewall therebetween, the step (f) being performed before the step (d).
In the method, the formation of the second sidewall improves a misalignment margin in step of forming an interconnect trench for the gate interconnect line.
Preferably, in the method, a dimension of the second sidewall formed in the step (f) in the direction of the gate length is greater than a dimension of the first sidewall in the direction of the gate length.
The method further improves the misalignment margin.
Preferably, the method further includes the steps of: (s) forming a pair of source/drain regions in the substrate, with a body region under the gate electrode disposed between the pair of source/drain regions; and (t) forming a contact plug in the interlayer insulation film, the contact plug being connected to the source/drain regions, the step (t) being performed in the same step as the step (e), wherein a dimension of the contact plug in the direction of the gate length is greater than the dimension of the gate interconnect line in the direction of the gate length.
The method reduces an etch rate difference when forming a contact hole for the contact plug and an interconnect trench for the gate interconnect line in the same etching step.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.